Thermal and Signal Integrity Co-Design and Verification of Embedded Cooling Structure With Thermal Transmission Line for High Bandwidth Memory Module-Reference-Cited by-同舟云学术

Thermal and Signal Integrity Co-Design and Verification of Embedded Cooling Structure With Thermal Transmission Line for High Bandwidth Memory Module

Published:2022-09 Issue:9 Volume:12 Page:1542-1556
ISSN:2156-3950
Container-title:IEEE Transactions on Components, Packaging and Manufacturing Technology
language:
Short-container-title:IEEE Trans. Compon., Packag. Manufact. Technol.

Author:

Son Keeyoung¹^ORCID,Kim Seongguk¹^ORCID,Park Hyunwook¹^ORCID,Shin Taein¹^ORCID,Kim Keunwoo¹^ORCID,Kim Minsu¹,Sim Boogyo¹^ORCID,Kim Subin²^ORCID,Park Gapyeol¹^ORCID,Park Shinyoung³^ORCID,Jeong Seungtaek⁴^ORCID,Kim Joungho¹^ORCID

Affiliation:

1. School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea

2. Samsung Electronics, Suwon, South Korea

3. Rambus, Seoul, South Korea

4. Electromagnetic Compatibility Laboratory, Missouri University of Science and Technology, Rolla, MO, USA

Funder

National Research Foundation of Korea Grant funded by the Korean Government

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Industrial and Manufacturing Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/5503870/9913798/09866738.pdf?arnumber=9866738

Reference33 articles.

1. A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits

2. High-frequency scalable electrical model and analysis of a through silicon via (TSV);kim;IEEE Trans Compon Packag Manuf Technol B,2011

3. Vertical tree 3-dimensional TSV clock distribution network in 3D IC

4. RAIDR

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