A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits-Reference-Cited by-同舟云学术

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A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits

Published:2015-01 Issue:1 Volume:50 Page:191-203
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Lee Dong Uk,Kim Kyung Whan,Kim Kwan Weon,Lee Kang Seol,Byeon Sang Jin,Kim Jae Hwan,Cho Jin Hee,Lee Jaejin,Chun Jun Hyun

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/6998099/06923498.pdf?arnumber=6923498

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2. Proposed package type for evaluating reliability of HBM Memory;Solid-State Electronics;2024-06

3. Present and Future, Challenges of High Bandwith Memory (HBM);2024 IEEE International Memory Workshop (IMW);2024-05-12

4. H3DM: A High-bandwidth High-capacity Hybrid 3D Memory Design for GPUs;Proceedings of the ACM on Measurement and Analysis of Computing Systems;2024-02-16

5. An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s;IEEE Journal of Solid-State Circuits;2023-11

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