Microstructure Development of Cu/SiO₂ Hybrid Bond Interconnects After Reliability Tests
Author:
Affiliation:
1. Institute of Electronic Packaging Technology, Technische Universität Dresden (TU Dresden), Dresden, Germany
2. All Silicon System Integration Dresden (ASSID), Fraunhofer Institute for Reliability and Microintegration IZM, Dresden, Germany
Funder
Department for Science and Arts of the Federal State of Saxony
Fraunhofer Society through the SAB Projects “Functional Integration for Micro-/Nano-Electronics”
“Transfer center: Functional Integration for the Micro-/Nano-Electronics”
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Industrial and Manufacturing Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/5503870/9743783/09706444.pdf?arnumber=9706444
Reference21 articles.
1. Wafer-level packaging and direct interconnection technology based on hybrid bonding and through silicon vias
2. Recent Developments in Fine Pitch Wafer-To-Wafer Hybrid Bonding with Copper Interconnect
3. Grain Structure Analysis of Cu/SiO2 Hybrid Bond Interconnects after Reliability Testing
4. Cu Microstructure of High Density Cu Hybrid Bonding Interconnection
5. Copper-to-copper direct bonding on highly (111)-oriented nanotwinned copper in no-vacuum ambient
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1. Reliability Challenges in Advanced 3D Technologies: The Case of Through Silicon Vias and SiCN–SiCN Wafer-to-Wafer Hybrid-Bonding Technologies;IEEE Transactions on Device and Materials Reliability;2023-12
2. 3D Integration via D2D Bump-Less Cu Bonding with Protruded and Recessed Topographies;ECS Journal of Solid State Science and Technology;2023-08-01
3. Recent progress on bumpless Cu/SiO2 hybrid bonding for 3D heterogeneous integration;Microelectronics International;2022-12-27
4. Novel Cu-nanowire-based technology enabling fine pitch interconnects for 2.5D/3D Integration;2022 IEEE 9th Electronics System-Integration Technology Conference (ESTC);2022-09-13
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