Warpage Prediction and Optimization for Wafer-Level Glass Interposer Packaging
Author:
Affiliation:
1. School of Mathematical Statistics and Mechanics, Beijing University of Technology, Beijing, China
2. School of Electronic Science and Engineering, Xiamen University, Xiamen, China
Funder
National Natural Science Foundation of China
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/5503870/10675732/10540590.pdf?arnumber=10540590
Reference24 articles.
1. A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing
2. Wafer Level System Integration of the Fifth Generation CoWoS®-S with High Performance Si Interposer at 2500 mm2
3. Physical Design Flow for 3D /CoWoS® Stacked IC s
4. Large-body-sized Glass-based Active Interposer for High-Performance Computing
5. Antennas in Glass Interposer For sub-THz Applications
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