Physical Design Flow for 3D /CoWoS® Stacked IC s-Reference-Cited by-同舟云学术

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Physical Design Flow for 3D /CoWoS® Stacked IC s

Published:2019-02-08 Issue: Volume: Page:81-114
ISSN:
Container-title:Handbook of 3D Integration
language:
Short-container-title:

Author:

Lin Yu‐Shiang,Goel Sandeep K.,Yuan Jonathan,Chen Tom,Lee Frank

Publisher

Wiley

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1002/9783527697052.ch5

Reference6 articles.

1. ISSCC(2014).ISSCC trend.

2. Stephens R. (2004).Jitter Analysis: The dual‐Dirac Model RJ/DJ andQ‐Scale. Retrieved fromhttps://www.keysight.com/upload/cmc_upload/All/dualdirac1.pdf.

3. JEDECJESD22‐C101E (2009).Field Induced Charged‐Device Model Test Method for Electrostatic Discharge Withstand Thresholds of Microelectronic Components.JEDEC.

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Warpage Prediction and Optimization for Wafer-Level Glass Interposer Packaging;IEEE Transactions on Components, Packaging and Manufacturing Technology;2024-08

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