Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors

Author:

Bhattacharjee Abhishek,Martonosi Margaret

Publisher

IEEE

Cited by 58 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28

2. Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28

3. Reconfigurable Virtual Memory for FPGA-Driven I/O;Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3;2023-03-25

4. FlexPointer: Fast Address Translation Based on Range TLB and Tagged Pointers;ACM Transactions on Architecture and Code Optimization;2023-03

5. Trans-FW: Short Circuiting Page Table Walk in Multi-GPU Systems via Remote Forwarding;2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2023-02

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