Reconfigurable Virtual Memory for FPGA-Driven I/O

Author:

Landgraf Joshua1,Giordano Matthew1,Yoon Esther1,Rossbach Christopher J.2

Affiliation:

1. University of Texas at Austin, USA

2. University of Texas at Austin, USA / Katana Graph, USA

Funder

National Science Foundation

National Nuclear Security Administration

Publisher

ACM

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3. Jeongseob Ahn , Seongwook Jin , and Jaehyuk Huh . 2015. Fast Two-Level Address Translation for Virtualized Systems . In IEEE TC. Jeongseob Ahn, Seongwook Jin, and Jaehyuk Huh. 2015. Fast Two-Level Address Translation for Virtualized Systems. In IEEE TC.

4. Alibaba Corp.. 2021. Alibaba Cloud Instances Overview. https://www.alibabacloud.com/help/doc-detail/108504.htm Alibaba Corp.. 2021. Alibaba Cloud Instances Overview. https://www.alibabacloud.com/help/doc-detail/108504.htm

5. Altera. [n. d.]. Integrating 100-GbE Switching Solutions on 28nm FPGAs. https://www.altera.com/en_US/pdfs/literature/wp/wp-01127-stxv-100gbe-switching.pdf (Accessed May 2018 ) Altera. [n. d.]. Integrating 100-GbE Switching Solutions on 28nm FPGAs. https://www.altera.com/en_US/pdfs/literature/wp/wp-01127-stxv-100gbe-switching.pdf (Accessed May 2018)

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Barre Chord: Efficient Virtual Memory Translation for Multi-Chip-Module GPUs;2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA);2024-06-29

2. Architectural Support for Sharing, Isolating and Virtualizing FPGA Resources;ACM Transactions on Architecture and Code Optimization;2024-05-21

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