Impact of LER on Mismatch in Nanosheet Transistors for 5nm-CMOS-Reference-Cited by-同舟云学术

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Impact of LER on Mismatch in Nanosheet Transistors for 5nm-CMOS

Published:2020-04 Issue: Volume: Page:
ISSN:
Container-title:2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
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Author:

Jha Chandan Kumar,Gupta Charu,Gupta Anshul,Vega Reinaldo A,Dixit Abhisek

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9110268/9117802/09117816.pdf?arnumber=9117816

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Scatterometry Critical Dimension Solution for Gate All Around Sheet-Specific Metrology: Topic/category: Advanced Metrology;2024 35th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC);2024-05-13

2. Novel Low-Power Floating-Point Divider With Linear Approximation and Minimum Mean Relative Error;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-12

3. Mueller matrix spectroscopy and physics-based machine learning for gate-all-around sheet-specific metrology;Metrology, Inspection, and Process Control XXXVII;2023-04-27

4. Benefits of Using Network Modeling Platforms When Studying IP Networks and Traffic Characterization;Computers;2023-02-16

5. Artificial Neural Network-Based Modeling for Estimating the Effects of Various Random Fluctuations on DC/Analog/RF Characteristics of GAA Si Nanosheet FETs;IEEE Transactions on Microwave Theory and Techniques;2022-11

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