Panel Level Packaging – Where are the Technology Limits?-Reference-Cited by-同舟云学术

Panel Level Packaging – Where are the Technology Limits?

Published:2022-05 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)
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Author:

Braun Tanja¹,Holck Ole¹,Obst Mattis¹,Voges Steve¹,Kahle Ruben¹,Bottcher Lars¹,Billaud Mathilde¹,Stobbe Lutz¹,Becker Karl-Friedrich¹,Aschenbrenner Rolf¹,Voitel Marcus²,Schein Friedrich-Leonhard²,Gerholt Lutz²,Schneider-Ramelow Martin²

Affiliation:

1. Fraunhofer Institute for Reliability and Microintegration,Berlin,Germany

2. Technical University Berlin,Berlin,Germany

Funder

Ministry of Education

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9816066/9816372/09816387.pdf?arnumber=9816387

Reference18 articles.

1. Adaptive Patterning Design Methodologies

2. Solving the Design and Verification Challenges of High Density Advanced Packaging;rinebold;Siemens Cadence Mentor Whitepaper,2017

3. Advances in Dry Etch Processing for High-Density Vertical Interconnects in Fan-Out Panel-Level Packaging and IC Substrates

4. DTCO including Sustainability: Power-Performance-Area-Cost-Environmental score (PPACE) Analysis for Logic Technologies

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