GIDL Analysis of 1T1C Structure for Sub-20nm DRAM Cell
Author:
Affiliation:
1. School of Electronic Science and Engineering, Xiamen University,Xiamen,China
Funder
National Key Research and Development Project
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9995719/9995746/09995836.pdf?arnumber=9995836
Reference16 articles.
1. A Novel 1T-1D DRAM Cell for Embedded Application
2. Novel Capacitorless Single-Transistor Charge-Trap DRAM (1T CT DRAM) Utilizing Electrons
3. Highly Scalable Saddle-Fin (S-Fin) Transistor for Sub-50nm DRAM Technology
4. Partial Isolation Type Buried Channel Array Transistor (Pi-BCAT) for a Sub-20 nm DRAM Cell Transistor
5. High-performance (EOT<0.4nm, Jg~10-7 A/Cm2) ALD-deposited Ru\SrTiO3 stack for next generations DRAM pillar capacitor;Popovici;2018 IEEE International Electron Devices Meeting (IEDM),2018
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