Highly Scalable Saddle-Fin (S-Fin) Transistor for Sub-50nm DRAM Technology-Reference-Cited by-同舟云学术

Highly Scalable Saddle-Fin (S-Fin) Transistor for Sub-50nm DRAM Technology

Published:2006 Issue: Volume: Page:
ISSN:
Container-title:2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.
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Author:

Sung-Wook Park ,Sung-Joo Hong ,Jin-Woong Kim ,Jae-Goan Jeong ,Kyung-Dong Yoo ,Seung-Chan Moon ,Hyun-Chul Sohn ,Noh-Jung Kwak ,Yun-Seok Cho ,Seung-Joo Baek ,Hyung-Soon Park ,Hyo Geun Yoon ,Bong-Hoon Lee ,Jin-Soo Kim ,Sun-Hwan Hwang ,Lae-Hee Lee ,Heung-Jae Cho ,Sung Yoon Cho ,Chai-O Chung ,Kwang-Ok Kim ,Min-Soo Yoo ,Se-Aug Jang ,Sang-Don Lee ,Sung-Woong Chung ,Sung-Wook Park ,Sung-Joo Hong ,Jin-Woong Kim ,Jae-Goan Jeong ,Kyung-Dong Yoo ,Seung-Chan Moon ,Hyun-Chul Sohn ,Noh-Jung Kwak ,Yun-Seok Cho ,Seung-Joo Baek ,Hyung-Soon Park ,Hyo Geun Yoon ,Bong-Hoon Lee ,Jin-Soo Kim ,Sun-Hwan Hwang ,Lae-Hee Lee ,Heung-Jae Cho ,Sung Yoon Cho ,Chai-O Chung ,Kwang-Ok Kim ,Min-Soo Yoo ,Se-Aug Jang ,Sang-Don Lee ,Sung-Woong Chung

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/11173/35986/01705202.pdf?arnumber=1705202

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