Suppression of Gate-Induced-Drain-Leakage Utilizing Local Polarization in Ferroelectric-Gate Field-Effect Transistors for DRAM Applications-Reference-Cited by-同舟云学术

Suppression of Gate-Induced-Drain-Leakage Utilizing Local Polarization in Ferroelectric-Gate Field-Effect Transistors for DRAM Applications

Published:2024-05 Issue:5 Volume:45 Page:813-816
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Kwak Been¹^ORCID,Lee Kitae²^ORCID,Kim Sihyun³^ORCID,Kwon Daewoong¹^ORCID

Affiliation:

1. Department of Electronic Engineering, Hanyang University, Seoul, South Korea

2. Department of Electrical and Computer Engineering and the Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea

3. Department of Electronic Engineering, Sogang University, Seoul, South Korea

Funder

National Research Foundation of Korea

Korea Government Ministry of Science and ICT

National Research and Development Program through the NRF

Ministry of Science and ICT, South Korea

MSIT, Korea, under the ITRC (Information Technology Research Center) support Program the IITP (Institute for Information and Communications Technology Planning and Evaluation

Samsung

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/55/10509537/10452269.pdf?arnumber=10452269

Reference20 articles.

1. Challenges for the DRAM cell scaling to 40nm

2. Challenges and future directions for the scaling of dynamic random-access memory (DRAM)

3. 20 nm DRAM: A new beginning of another revolution;Park

4. A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

5. Impact of gate-induced drain leakage on retention time distribution of 256 Mbit DRAM with negative wordline bias