Hardware-Based Ternary Neural Network Using AND-Type Poly-Si TFT Array and Its Optimization Guideline-Reference-Cited by-同舟云学术

Hardware-Based Ternary Neural Network Using AND-Type Poly-Si TFT Array and Its Optimization Guideline

Published:2023-08 Issue:8 Volume:70 Page:4206-4212
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Kwon Dongseok¹^ORCID,Park Min-Kyu¹^ORCID,Kang Won-Mook¹^ORCID,Hwang Joon¹^ORCID,Koo Ryun-Han¹,Bae Jong-Ho²^ORCID,Lee Jong-Ho³^ORCID

Affiliation:

1. School of Electrical and Computer Engineering and Inter-University Semiconductor Research Center (ISRC), Seoul National University, Seoul, South Korea

2. School of Electrical Engineering, Kookmin University, Seoul, South Korea

3. Ministry of Science and ICT, Sejong-si, South Korea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/10194493/10171236.pdf?arnumber=10171236

Reference33 articles.

1. High-Throughput In-Memory Computing for Binary Deep Neural Networks With Monolithically Integrated RRAM and 90-nm CMOS

2. A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References

3. In situ training of feed-forward and recurrent convolutional memristor networks

4. Efficient and self-adaptive in-situ learning in multilayer memristor neural networks

5. Highly Reliable Inference System of Neural Networks Using Gated Schottky Diodes

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