A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References
Author:
Affiliation:
1. School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA
2. Taiwan Semiconductor Manufacturing Company (TSMC), San Jose, CA, USA
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
https://ieeexplore.ieee.org/ielam/4/9866858/9755965-aam.pdf
Reference37 articles.
1. Investigation of Read Disturb and Bipolar Read Scheme on Multilevel RRAM-Based Deep Learning Inference Engine
2. Impact of Non-Ideal Characteristics of Resistive Synaptic Devices on Implementing Convolutional Neural Networks
3. DNN+NeuroSim: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators with Versatile Device Technologies
4. Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning
5. A Variation Robust Inference Engine Based on STT-MRAM with Parallel Read-Out
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4. Write–Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-02
5. Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip;IEEE Journal of Solid-State Circuits;2024-02
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