A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References

Author:

Li Wantong1ORCID,Sun Xiaoyu2ORCID,Huang Shanshi1ORCID,Jiang Hongwu1ORCID,Yu Shimeng1ORCID

Affiliation:

1. School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA

2. Taiwan Semiconductor Manufacturing Company (TSMC), San Jose, CA, USA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 24 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Write System for Compact RRAM Memory Arrays Based on F-1T1R;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. Dynamic Detection and Mitigation of Read-disturb for Accurate Memristor-based Neural Networks;2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS);2024-04-22

3. Hardware implementation of memristor-based artificial neural networks;Nature Communications;2024-03-04

4. Write–Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-02

5. Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip;IEEE Journal of Solid-State Circuits;2024-02

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