Impact of Bottom Dielectric Isolation of Si-Stacked Nanosheet Transistor on Stress and Self-Heating at 3-nm Node and Beyond
Author:
Affiliation:
1. Nanotechnology and Nanoelectronics Program, Zewail City of Science and Technology, Giza, Egypt
2. Electrical Engineering Department, College of Engineering and Information Technology, Ajman University, Ajman, United Arab Emirates
Funder
Zewail City of Science and Technology and Ajman University’s internal
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/10294316/10271258.pdf?arnumber=10271258
Reference39 articles.
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2. Experimental Investigation of Size Effects on the Thermal Conductivity of Silicon-Germanium Alloy Thin Films
3. 3D Monte Carlo simulation of FinFET and FDSOI devices with accurate quantum correction
4. Self-Heating Mitigation of TreeFETs by Interbridges
5. Unified apparent bandgap narrowing in n- and p-type silicon;klaassen;Solid State Electron,1992
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