CIS: Conditional Importance Sampling for Yield Optimization of Analog and SRAM Circuits
Author:
Affiliation:
1. Beihang University,School of Integrated Circuit Science and Engineering,Beijing,China
2. University of Sheffield,School of Mathematics and Statistics,UK,S3 7RH
Funder
Fundamental Research Funds for the Central Universities
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10473777/10473787/10473819.pdf?arnumber=10473819
Reference15 articles.
1. Efficient and Accurate Statistical Analog Yield Optimization and Variation-Aware Circuit Sizing Based on Computational Intelligence Techniques
2. Efficient Yield Optimization for Analog and SRAM Circuits via Gaussian Process Regression and Adaptive Yield Estimation
3. Breaking the simulation barrier: SRAM evaluation through norm minimization
4. A fast and robust failure analysis of memory circuits using adaptive importance sampling method
5. Adaptive Clustering and Sampling for High-Dimensional and Multi-Failure-Region SRAM Yield Analysis
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