InP DHBT-Based Monolithically Integrated CDR/DEMUX IC Operating at 80 Gbit/s-Reference-Cited by-同舟云学术

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InP DHBT-Based Monolithically Integrated CDR/DEMUX IC Operating at 80 Gbit/s

Published:2006-10 Issue:10 Volume:41 Page:2215-2223
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Makon R.E.¹,Driad R.,Schneider K.,Ludwig M.,Aidam R.,Quay R.,Schlechtweg M.,Weimann G.

Affiliation:

1. IAF, Fraunhofer Inst. of Appl. Solid-State Phys., Freiburg

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/35952/01703675.pdf?arnumber=1703675

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 56 GHz InP VCO for Use in 112 GBaud (112 GBit/s NRZ or 224 GBit/s PAM-4) InP Integrated Optical Receiver Front-End CDR Block;2023 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE);2023-09-24

2. High-Bitrate-Measurement-System-Oriented Lower-Jitter 113-Gbit/s 2:1 Multiplexer and 1:2 Demultiplexer Modules Using 1-µm InP/InGaAs/InP Double Heterojunction Bipolar Transistors;IEICE Transactions on Electronics;2013

3. InP-based heterojunction bipolar transistors with InGaAs/GaAs strained-layer-superlattice;Applied Physics Letters;2011-01-24

4. Improved Design and Characterization Method for Very High Speed Bipolar Circuits;2008 Global Symposium on Millimeter Waves;2008-04

5. Low-Power Circuits for a 2.5-V, 10.7-to-86-Gb/s Serial Transmitter in 130-nm SiGe BiCMOS;IEEE Journal of Solid-State Circuits;2007-10

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