Bidirectional Precharge and Negative Bias Scheme for Program Disturbance Suppression in 3-D NAND Flash Memory
Author:
Affiliation:
1. Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South Korea
2. Memory Division, Samsung Electronics Company Ltd., Hwaseong, South Korea
Funder
Semiconductor Industry Collaborative Project between POSTECH and SAMSUNG Electronics
Technology Innovation Program
Ministry of Trade, Industry and Energy (MOTIE), South Korea
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/10328902/10299544.pdf?arnumber=10299544
Reference22 articles.
1. Leakage characterization of top select transistor for program disturbance optimization in 3D NAND flash
2. A Novel Program Scheme for Program Disturbance Optimization in 3-D NAND Flash Memory
3. A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme;suh;IEEE J Solid-State Circuits,1995
4. Analysis on Program Disturbance in Channel-Stacked NAND Flash Memory With Layer Selection by Multilevel Operation
5. A Novel Program Operation Scheme With Negative Bias in 3-D NAND Flash Memory
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