Leakage characterization of top select transistor for program disturbance optimization in 3D NAND flash-Reference-Cited by-同舟云学术

Leakage characterization of top select transistor for program disturbance optimization in 3D NAND flash

Published:2018-03 Issue: Volume:141 Page:18-22
ISSN:0038-1101
Container-title:Solid-State Electronics
language:en
Short-container-title:Solid-State Electronics

Author:

Zhang Yu^ORCID,Jin Lei,Jiang Dandan,Zou Xingqi,Zhao Zhiguo,Gao Jing,Zeng Ming,Zhou Wenbin,Tang Zhaoyun,Huo Zongliang

Funder

National Natural Science Foundation of China

Key project of Sichuan provincial Education Department

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference19 articles.

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2. New scaling limitation of the floating gate cell in NAND flash memory;Kim;IRPS,2010

3. A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND flash using junction-free buried channel BE-SONOS device;Lue;VLSI Technol,2010

4. Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices;Katsumata;VLSI Technol,2009

5. Vertical cell array using TCAT (Terabit Cell Array Transistor) technology for ultra high density NAND flash memory;Jang;VLSI Technol,2009

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