High-Performance Algorithm Adaptations and Hardware Architecture for HEVC Intra Encoders
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Media Technology
Link
http://xplorestaging.ieee.org/ielx7/76/8751741/08701479.pdf?arnumber=8701479
Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Parallelized RDOQ Algorithm and Fully Pipelined Hardware Architecture for AVS3 Video Coding;IEEE Transactions on Circuits and Systems for Video Technology;2024-07
2. HEVC Intra Prediction Acceleration Algorithm Based on Image Texture;2024 6th International Conference on Communications, Information System and Computer Engineering (CISCE);2024-05-10
3. A Reconfigurable implement of the Chroma Intra-frame linear Prediction Algorithm;2023 6th International Conference on Artificial Intelligence and Pattern Recognition (AIPR);2023-09-22
4. Hardware Architecture for Realtime HEVC Intra Prediction;Electronics;2023-04-04
5. DMPRA: A Dynamic Reconfiguration Mechanism for a Dual-Mode Programmable Reconfigurable Array Architecture;Journal of Circuits, Systems and Computers;2022-12-10
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