Affiliation:
1. Computer Engineering Department, University of Information Technology, Ho Chi Minh City 700000, Vietnam
2. Vietnam National University, Ho Chi Minh City 700000, Vietnam
Abstract
Researchers have, in recent times, achieved excellent compression efficiency by implementing a more complicated compression algorithm due to the rapid development of video compression. As a result, the next model of video compression, High-Efficiency Video Coding (HEVC), provides high-quality video output while requiring less bandwidth. However, implementing the intra-prediction technique in HEVC requires significant processing complexity. This research provides a completely pipelined hardware architecture solution capable of real-time compression to minimize computing complexity. All prediction unit sizes of 4×4, 8×8, 16×16, and 32×32, and all planar, angular, and DC modes are supported by the proposed solution. The synthesis results mapped to Xilinx Virtex 7 reveal that our solution can do real-time output with 210 frames per second (FPS) at 1920×1080 resolution, called Full High Definition (FHD), or 52 FPS at 3840×2160 resolution, called 4K, while operating at 232 Mhz maximum frequency.
Funder
VNUHCM-University of Information Technology’s Scientific Research Support Fund
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering