Author:
Rajaraman R.,Kim J.S.,Vijaykrishnan N.,Xie Y.,Irwin M.J.
Cited by
31 articles.
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1. A Holistic Approach for Characterization of SET Effects in a Standard Digital Cell Library;2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS);2024-02-27
2. Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis;2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2023-10-03
3. Accurate Soft Error Rate Evaluation Using Event-Driven Dynamic Timing Analysis;2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2023-10-03
4. A Learning-Based Approach for Single Event Transient Analysis in Pass Transistor Logic;2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS);2023-07-03
5. Modeling of single/multiple-bit upset effects on logic circuits applying Recurrent Neural Network;Microelectronics Journal;2021-11