Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis-Reference-Cited by-同舟云学术

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Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis

Published:2023-10-03 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
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Author:

Georgakidis Christos¹,Valiantzas Dimitris¹,Simoglou Stavros¹,Lilitsis Iordanis¹,Chatzivangelis Nikolaos¹,Golfos Ilias¹,Andjelkovic Marko²,Sotiriou Christos¹,Krstic Milos²

Affiliation:

1. University of Thessaly,Department of Electrical and Computer Engineering,Greece

2. IHP - Leibniz Institut für Innovative Mikroelektronik,Germany

Funder

University of Thessaly

Hellenic Foundation for Research and Innovation

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10313343/10313345/10313533.pdf?arnumber=10313533

Reference19 articles.

1. Accelerated Soft-Error-Rate (SER) Estimation for Combinational and Sequential Circuits

2. SEAT-LA: a soft error analysis tool for combinational logic

3. CASSER: A Closed-Form Analysis Framework for Statistical Soft Error Rate

4. Fast and Accurate SER Estimation for Large Combinational Blocks in Early Stages of the Design

5. Soft-Error-Rate-Analysis (SERA) Methodology

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