Author:
Tschanz J.,Narendra S.,Zhanping Chen ,Borkar S.,Sachdev M.,Vivek De
Cited by
65 articles.
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1. High speed ultra-low-lower lulse-triggered JLFET Flip-Flop;Modern Physics Letters B;2023-10-19
2. Low-Power Redundant-Transition-Free TSPC Dual-Edge-Triggering Flip-Flop Using Single-Transistor-Clocked Buffer;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-05
3. Study of finfet transistor: critical and literature review in finfet transistor in the active filter;3C TIC: Cuadernos de desarrollo aplicados a las TIC;2023-03-31
4. Improved Design and Comparison of a Low Power CNTFET based on D Flip-Flop;2023 International Conference on Electrical, Computer and Communication Engineering (ECCE);2023-02-23
5. An Architecture of a True Single Phase Clock D Flip-flop utilizing 45nm Technology;2022 Second International Conference on Advanced Technologies in Intelligent Control, Environment, Computing & Communication Engineering (ICATIECE);2022-12-16