Improved Design and Comparison of a Low Power CNTFET based on D Flip-Flop-Reference-Cited by-同舟云学术

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Improved Design and Comparison of a Low Power CNTFET based on D Flip-Flop

Published:2023-02-23 Issue: Volume: Page:
ISSN:
Container-title:2023 International Conference on Electrical, Computer and Communication Engineering (ECCE)
language:
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Author:

Ridoy Jahid Hasan¹,Rahman Atik Yasir²,Saquib Fahad Raihan³

Affiliation:

1. Ahsanullah University of Science and Technology,Department of Electrical & Electronic Engineering,Dhaka,Bangladesh

2. The University of Tennessee, Knoxville,Department of Electrical Engineering and Computer Science,Knoxville,Tennessee,United States

3. University of Scholars,Department of Electrical and Electronic Engineering,Dhaka,Bangladesh

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10101485/10100742/10101615.pdf?arnumber=10101615

Reference13 articles.

1. Comparative delay and energy of single edge-triggered and dual edge-triggered pulsed flip-flops for high-performance microprocessors

2. Low-power single- and double-edge-triggered flip-flops for high-speed applications

3. Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through

4. Ultra-Low Power Pulse-Triggered CNTFET-Based Flip-Flop

5. A review on carbon nanotube field effect transistors (CNTFETs) for ultra-low power applications

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of Low Power Ternary Logic Encoder and ADC using CNTFET;WSEAS TRANSACTIONS ON ELECTRONICS;2024-04-22

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