An Architecture of a True Single Phase Clock D Flip-flop utilizing 45nm Technology
Author:
Affiliation:
1. Jain University,Department of Computer Science and Engineering,Bangalore,India
2. Teerthanker Mahaveer University,Department of Electronics & Communication Engineering,Moradabad,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10046660/10046669/10046670.pdf?arnumber=10046670
Reference15 articles.
1. Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
2. A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application
3. Flow-through latch and edge-triggered flip-flop hybrid elements
4. Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
5. High-performance and low-power conditional discharge flip-flop
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