High speed ultra-low-lower lulse-triggered JLFET Flip-Flop

Abstract

Power efficiency and enhancing the speed are two major challenges of traditional D-Flip-Flops (D-FF) for designing energy-efficient IOT (internet of thing) devices. Therefore, the main objective of this research article is to design low power high speed D-FF circuits using emerging nanoscale devices. Hence, the first time, in this paper, a pulse-triggered Junctionless D-Flip-Flop (JLFET D-FF) circuit is presented using 15 nm technology, targeting both power budget and high performance concerns. Here, the D-FF circuit uses a signal feedthrough approach to minimize transition duration when output switches from 0 to 1, which requires only a single JLFET structure. Further, to minimize the delay time for the 1 to 0 transition, the discharging path is optimized by employing only two JLFETs. The novel JLFET D-FF circuit is simulated in the Cadence virtuoso simulator using the Verilog-A model. The simulated results have shown that the average power consumption and delay of the proposed circuit are significantly improved as compared to the earlier reported work. The average power consumption in JLFET D-FF for 25% data switching activity is improved by approximately 56% and 64% than ULPFF and SFT-FF, respectively. Further, the power delay performance (PDP) of JLFET D-FF is improved by 96% and 97% at the same data switching activity as compared to ULPFF and SFT-FF, respectively. The performance of the novel D-FF circuit is measured by considering D to Q delay as key parameter which is improved by 77% and 77.5% than ULPFF and SFT-FF, respectively. The simulation results of this work can give insights into the in-circuit behavior of modern semiconductor devices.