A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector
Author:
Affiliation:
1. University of Macau,State Key Laboratory of Analog and Mixed-Signal VLSI and IME/FST-ECE,Macao,China
2. Institute of Semiconductors, Chinese Academy of Sciences,Beijing,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9933920/9934110/09934542.pdf?arnumber=9934542
Reference50 articles.
1. A 3.65 mW 5 bit 2GS/s flash ADC with built-in reference voltage in 65nm CMOS process
2. Comparator with built-in reference voltage generation and split-ROM encoder for a high-speed flash ADC
3. 0.6–2.7-Gb/s Referenceless Parallel CDR With a Stochastic Dispersion-Tolerant Frequency Acquisition Technique
4. A 3x9 Gb/s Shared, All-Digital CDR for High-Speed, High-Density I/O
5. A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS
Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-07
2. A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation;International Journal of Circuit Theory and Applications;2023-01-04
3. A 0.2–7.1-Gb/s Low-Jitter Full-Rate Reference-Less CDR for Communication Signal Analyzers;IEEE Transactions on Instrumentation and Measurement;2023
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