A 0.2–7.1-Gb/s Low-Jitter Full-Rate Reference-Less CDR for Communication Signal Analyzers-Reference-Cited by-同舟云学术

A 0.2–7.1-Gb/s Low-Jitter Full-Rate Reference-Less CDR for Communication Signal Analyzers

Published:2023 Issue: Volume:72 Page:1-8
ISSN:0018-9456
Container-title:IEEE Transactions on Instrumentation and Measurement
language:
Short-container-title:IEEE Trans. Instrum. Meas.

Author:

Meng Xiangyu¹^ORCID,Xie Wang¹^ORCID,Zhang Jiaqi¹^ORCID,Zhang Zhao²^ORCID

Affiliation:

1. School of Electronics and Information Technology, Sun Yat-sen University, Guangzhou, China

2. State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing, China

Funder

National Natural Science Foundation of China

Basic and Applied Basic Research Foundation of Guangdong Province

Fundamental Research Funds for the Central Universities, Sun Yat-sen University

National Key Research and Development Program of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Instrumentation

Link

http://xplorestaging.ieee.org/ielx7/19/10012124/10038505.pdf?arnumber=10038505

Reference18 articles.

1. A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier

2. A 0.5-to-32.75 Gb/s flexible-reach wireline transceiver in 20 nm CMOS;upadhyaya;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2015

3. A 12 Gb/s 0.9 mW/Gb/s Wide-Bandwidth Injection-Type CDR in 28 nm CMOS With Reference-Free Frequency Capture

4. A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization

5. 3.2 multi-standard 185 fsrms 0.3-to-28 Gb/s 40 dB backplane signal conditioner with adaptive pattern-match 36-tap DFE and data-rate-adjustment PLL in 28 nm CMOS;kawamoto;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2015

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