A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization-Reference-Cited by-同舟云学术

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A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization

Published:2016-02 Issue:2 Volume:63 Page:276-287
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Choi Seungnam,Son Hyunwoo,Shin Jongshin,Lee Sang-Hyun,Kim Byungsub,Park Hong-June,Sim Jae-Yoon

Funder

Institute for Information & communications Technology Promotion

Korean government (MSIP)

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/7434668/7426782.pdf?arnumber=7426782

Cited by 23 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 1.4-8 Gb/s Low Power Quarter-Rate Single-Loop Referenceless CDR With Unlimited Capture Range;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-09

2. A Linearity Improved Equalizers for Short-Channel Communication Links;2024 35th Irish Signals and Systems Conference (ISSC);2024-06-13

3. Design of a Low-Jitter 5.4 Gbps Half-Rate Clock and Data Recovery Circuit for eDP Application;2024 10th International Conference on Applied System Innovation (ICASI);2024-04-17

4. A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-07

5. A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation;International Journal of Circuit Theory and Applications;2023-01-04

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