A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier-Reference-Cited by-同舟云学术

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A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier

Published:2017-06 Issue:6 Volume:64 Page:650-654
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Kim Ja-Young,Song Junyoung,You Jungtaek,Hwang Sewook,Bae Sang-Geun,Kim Chulwoo

Funder

National Research Foundation of Korea (NRF)

Korea Government (MEST)

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/7934201/07337379.pdf?arnumber=7337379

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 1.4-8 Gb/s Low Power Quarter-Rate Single-Loop Referenceless CDR With Unlimited Capture Range;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-09

2. A 0.7-pJ/b 12.5-Gb/s Reference-Less Subsampling Clock and Data Recovery Circuit;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-06

3. A 0.2–7.1-Gb/s Low-Jitter Full-Rate Reference-Less CDR for Communication Signal Analyzers;IEEE Transactions on Instrumentation and Measurement;2023

4. A 9.8–12.5 Gb/s Low-Jitter Reference-Less Clock and Data Recovery Circuit;Journal of Circuits, Systems and Computers;2022-04-04

5. Pseudo-Reference Counter-Based FLL for 6 Gb/s Reference-Less CDR in 65-nm CMOS;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-04

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