Pseudo-Reference Counter-Based FLL for 6 Gb/s Reference-Less CDR in 65-nm CMOS
Author:
Affiliation:
1. Department of Electronics Engineering, Kwangwoon University, Seoul, South Korea
2. Electrical and Computer Engineering Department, University of Minnesota, Minneapolis, MN, USA
Funder
Research Grant of Kwangwoon University
IC Design Education Center
National Research Foundation of Korea
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/9741739/09687835.pdf?arnumber=9687835
Reference16 articles.
1. An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang–Bang Phase-Frequency Detection
2. A low-noise phase-locked loop design by loop bandwidth optimization;lim;IEEE J Solid-State Circuits,2000
3. Phase noise in oscillators: a unifying theory and numerical methods for characterization
4. Analysis of a frequency acquisition technique with a stochastic reference clock generator;han;IEEE Trans Circuits Syst II Exp Briefs,2012
5. A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy
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