Nanowire TFET with different Source Compositions applied to Low-Dropout Voltage Regulator
Author:
Affiliation:
1. LSI/PSI/USP, University of Sao Paulo,Sao Paulo,Brazil
Funder
CNPq
CAPES
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9880925/9880936/09881035.pdf?arnumber=9881035
Reference21 articles.
1. Full On-Chip CMOS Low-Dropout Voltage Regulator
2. Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction Tunnel-FETs
3. Impact of process and geometrical parameters on the electrical characteristics of vertical nanowire silicon n-TFETs
4. Tunnel field-effect transistor without gate-drain overlap
5. Investigation on the Effects of Gate-Source Overlap/Underlap and Source Doping Gradient of n-Type Si Cylindrical Gate-All-Around Tunnel Field-Effect Transistors
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1. Analysis of Low-Dropout Voltage Regulator designed with Gate-All-Around nanosheet transistors;2023 37th Symposium on Microelectronics Technology and Devices (SBMicro);2023-08-28
2. Hybrid low-dropout voltage regulator designed with TFET-MOSFET nanowire technologies;Semiconductor Science and Technology;2023-08-18
3. Comparison of low-dropout voltage regulators designed with line and nanowire tunnel-FET experimental data including a simple process variability analysis;Solid-State Electronics;2023-04
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