Sub-500-ps 64-b ALUs in 0.18-μm SOI/bulk CMOS: design and scaling trends-Reference-Cited by-同舟云学术

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Sub-500-ps 64-b ALUs in 0.18-μm SOI/bulk CMOS: design and scaling trends

Published:2001 Issue:11 Volume:36 Page:1636-1646
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Mathew S.K.,Krishnamurthy R.K.,Anders M.A.,Rios R.,Mistry K.R.,Soumyanath K.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/20772/00962283.pdf?arnumber=962283

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3. A framework for high-speed parallel-prefix adder performance evaluation and comparison;International Journal of Circuit Theory and Applications;2014-09-09

4. Partially depleted (PD) silicon-on-insulator (SOI) technology: circuit solutions;Silicon-On-Insulator (SOI) Technology;2014

5. Noise-immune dual-rail dynamic circuit for wide fan-in gates in asynchronous designs;IEEJ Transactions on Electrical and Electronic Engineering;2012-09-18

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