A framework for high-speed parallel-prefix adder performance evaluation and comparison-Reference-Cited by-同舟云学术

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A framework for high-speed parallel-prefix adder performance evaluation and comparison

Published:2014-09-09 Issue:10 Volume:43 Page:1474-1490
ISSN:0098-9886
Container-title:International Journal of Circuit Theory and Applications
language:en
Short-container-title:Int. J. Circ. Theor. Appl.

Author:

Hobson Richard F.¹

Affiliation:

1. School of Engineering Science; Simon Fraser University; Burnaby B.C. V5A 1S6 Canada

Funder

CMC Microsystems Corp

NSERC of Canada

Publisher

Wiley

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Science Applications,Electronic, Optical and Magnetic Materials

Reference34 articles.

1. A 9-GHz 65-nm Intel Pentium 4 processor integer execuion unit;Wijeratno;IEEE Journal of Solid-State Circuits,2007

2. A 4-GHz 300 mW 64-bit integer execution ALU with dual supply voltages in 90 nm CMOS;Mathew;IEEE Journal of Solid-State Circuits,2005

3. Zhou C Fleischer BM Gschwind M Puri R 64-bit prefix adders: power-efficient topologies and design solutions IEEE Custom Integrated Circuits Conf. Proceedings 2009 179 182

4. Sub-500-ps 64-b ALUs in 0.18-um SOI/bulk CMOS: design and scaling trends;Mathew;IEEE Journal of Solid-State Circuits,2001

5. A 1.0-GHz single-issue 64-bit PowerPC integer processor;Silberman;IEEE Journal of Solid-State Circuits,1998

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A novel generic modulo‐2 graph with full set taxonomical conversion to parallel prefix adders;International Journal of Circuit Theory and Applications;2022-01-03

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