Author:
Zhou Ching,Fleischer Bruce M.,Gschwind Michael,Puri Ruchir
Cited by
7 articles.
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1. Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2019-12
2. A Number System Approach for Adder Topologies;2017 IEEE 24th Symposium on Computer Arithmetic (ARITH);2017-07
3. Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2016-05
4. Structured Digital Design;Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology;2016-04-14
5. Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2014-10