A 0.5 V 10 b 3 MS/s 2-then-1b/cycle SAR ADC with Digital-based Time-Domain Reference and Dual-Mode Comparator-Reference-Cited by-同舟云学术

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A 0.5 V 10 b 3 MS/s 2-then-1b/cycle SAR ADC with Digital-based Time-Domain Reference and Dual-Mode Comparator

Published:2021 Issue: Volume: Page:1-1
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Jung Dong-Kyu,Seong Kiho,Han Jae-Soub,Shim Yong,Baek Kwang-Hyun

Funder

IC Design Education Center

ChungAng University

Ministry of Science and ICT South Korea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/4358609/09606183.pdf?arnumber=9606183

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 0.5 V 10-bit SAR ADC with offset calibrated time-domain comparator;AEU - International Journal of Electronics and Communications;2024-05

2. A 12-Bit SAR ADC with Binary Search Calibration Algorithm for a Split Capacitor;Electronics;2024-01-19

3. A reconfigurable 8-to-12-b 10-MS/s energy-efficient two-step ADC;Microelectronics Journal;2023-07

4. A Time-Based CMOS Readout Circuit for Amperometric Biosensors;2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2023-06-18

5. Recent Advances and Trends in Voltage-Time Domain Hybrid ADCs;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-06

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