A 0.5 V 10-bit SAR ADC with offset calibrated time-domain comparator-Reference-Cited by-同舟云学术

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A 0.5 V 10-bit SAR ADC with offset calibrated time-domain comparator

Published:2024-05 Issue: Volume:178 Page:155261
ISSN:1434-8411
Container-title:AEU - International Journal of Electronics and Communications
language:en
Short-container-title:AEU - International Journal of Electronics and Communications

Author:

Wang Yadong^ORCID,Zhan Yi,Qiao Shushan,Hu Xiaoyu

Publisher

Elsevier BV

Reference35 articles.

1. Liou CY, Hsieh CC. A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS. In: 2013 IEEE international solid-state circuits conference digest of technical papers; 2013. p. 280–1. doi: 10.1109/ISSCC.2013.6487735.

2. A 0.5 V 10 b 3 MS/s 2-Then-1b/cycle SAR ADC with digital-based time-domain reference and dual-mode comparator;Jung;IEEE Trans Circuits Syst Express Briefs,2022

3. An early shutdown circuit for power reduction in high-precision dynamic comparators;Shahpari;AEU-Int J Electron C,2020

4. All-MOS charge redistribution analog-to-digital conversion techniques. I;McCreary;IEEE J Solid State Circuits,1975

5. A reliable bubble sorting calibration method for SAR ADC;Fan;AEU-Int J Electron C,2020

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