Recent Advances and Trends in Voltage-Time Domain Hybrid ADCs
Author:
Affiliation:
1. Shaanxi Key Laboratory of Integrated Circuits and Systems, School of Microelectronics, Xidian University, Xi’an, China
Funder
National Natural Science Foundation of China
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/9786589/09763855.pdf?arnumber=9763855
Reference67 articles.
1. A 280MS/s 12b SAR-Assisted Hybrid ADC with Time Domain Sub-Range Quantizer in 45nm CMOS
2. A Two-Step ADC With Statistical Calibration
3. A Two-Stage ADC Architecture With VCO-Based Second Stage
4. A 2.02–5.16 fJ/conversion step 10 bit hybrid coarse-fine SAR ADC with time-domain quantizer in 90 nm CMOS;chen;IEEE J Solid-State Circuits,2016
5. A 0.5–1.1-V Adaptive Bypassing SAR ADC Utilizing the Oscillation-Cycle Information of a VCO-Based Comparator
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4. An 800 kS/s 1.83 fJ/conv. 12b ADC via Voltage Successive Approximation and Gated Cyclic Vernier Time Digitization;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
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