A 0.45 pJ/b 24 Gb/s NRZ Receiver Data-Path Using Half-Baud-Rate Duobinary Sampling-Reference-Cited by-同舟云学术

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A 0.45 pJ/b 24 Gb/s NRZ Receiver Data-Path Using Half-Baud-Rate Duobinary Sampling

Published:2024-09 Issue:9 Volume:71 Page:4096-4100
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Park Seungwoo¹,Choi Yoonjae²^ORCID,Choi Jonghyuck²^ORCID,Sim Jincheol²^ORCID,Kwon Youngwook²^ORCID,Sim Changmin¹^ORCID,Kim Seongcheol¹^ORCID,Kim Chulwoo²^ORCID

Affiliation:

1. Department of Semiconductor System Engineering, Korea University, Seoul, South Korea

2. Department of Electrical Engineering, Korea University, Seoul, South Korea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/8920/10666887/10474174.pdf?arnumber=10474174

Reference14 articles.

1. A 32Gb/s wireline receiver with a low-frequency equalizer, CTLE and 2-tap DFE in 28nm CMOS

2. A 25mW Highly Linear Continuous-Time FIR Equalizer for 25Gb/s Serial Links in 28-nm CMOS

3. A 40-Gb/s 14-mW CMOS Wireline Receiver

4. A 25 Gb/s Wireline Receiver With Feedforward and Feedback Equalizers at Analog Front-End

5. A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface

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