A 40-Gb/s 14-mW CMOS Wireline Receiver
Author:
Funder
Texas Instruments
Realtek Semiconductor
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/4/8015205/07939955.pdf?arnumber=7939955
Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 0.45 pJ/b 24 Gb/s NRZ Receiver Data-Path Using Half-Baud-Rate Duobinary Sampling;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-09
2. A Sub-Baud-Rate Wireline Receiver With One-Tap DFE;IEEE Journal of Solid-State Circuits;2024
3. A 32 Gb/s NRZ PI-Based Baud-Rate Digitial Clock and Data Recovery Circuit in 28nm CMOS Technology;2023 8th International Conference on Integrated Circuits and Microsystems (ICICM);2023-10-20
4. Design Techniques for CMOS Wireline NRZ Receivers Up To 56 Gb/s;IEEE Open Journal of the Solid-State Circuits Society;2023
5. Breaking the Speed-Power Tradeoffs in Broadband Circuits: Reviewing design techniques for transceivers up to 56 GHz;IEEE Nanotechnology Magazine;2022-06
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