Breaking the Speed-Power Tradeoffs in Broadband Circuits: Reviewing design techniques for transceivers up to 56 GHz
Author:
Affiliation:
1. Electrical and Computer Engineering Department, University of California, Los Angeles, California, USA
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Mechanical Engineering
Link
http://xplorestaging.ieee.org/ielx7/4451717/9779660/09754321.pdf?arnumber=9754321
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1. A 1.2 Gbps CMOS DFE receiver with the extended sampling time window for application to the SSTL channel
2. A 1-Tap 40-Gb/s Look-Ahead Decision Feedback Equalizer in 0.18-$muhbox m$SiGe BiCMOS Technology
3. A 56-GHz fractional-N 22-mW PLL;zhao;Proc IEEE Int Solid-State Circuits Conf,0
4. A 4.9pJ/b 16-to-64Gb/s PAM-4 VSR transceiver in 28nm FDSOI CMOS
5. 6.1 A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET
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