A 25 Gb/s Wireline Receiver With Feedforward and Feedback Equalizers at Analog Front-End-Reference-Cited by-同舟云学术

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A 25 Gb/s Wireline Receiver With Feedforward and Feedback Equalizers at Analog Front-End

Published:2022-02 Issue:2 Volume:69 Page:404-408
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Sim Jincheol,Lee Yeonho^ORCID,Park Hyunsu,Choi Yoonjae^ORCID,Choi Jonghyuck^ORCID,Kim Chulwoo^ORCID

Funder

Future Interconnect Technology Cluster Program of Samsung Electronics

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/9695534/09469785.pdf?arnumber=9469785

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 0.45 pJ/b 24 Gb/s NRZ Receiver Data-Path Using Half-Baud-Rate Duobinary Sampling;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-09

2. Trade-Offs in Design of Wide-Band Inverter-Based Amplifiers;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-07

3. A 10-Gb/s Wireline Receiver Using Linear Baud-Rate CDR and Analog Equalizer for Free Space Optical Communication Over 10- and 100-m Distances;IEEE Journal of Solid-State Circuits;2024-06

4. Artificial Neural Network Based on Memristive Circuit for High-Speed Equalization;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-04

5. A High Efficiency 14–28 Gb/s Tunable Receiver Analog Front-End in 65 nm CMOS Technology;Journal of Circuits, Systems and Computers;2023-10-28

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