A High Efficiency 14–28 Gb/s Tunable Receiver Analog Front-End in 65 nm CMOS Technology

Abstract

This work presents a tunable receiver analog front-end (AFE) circuit, capable of achieving data rates between 14 Gb/s and 28 Gb/s. The circuit is implemented using the TSMC 65 nm CMOS technology. The circuit incorporates a continuous-time linear equalizer (CTLE), a transimpedance amplifier (TIA) and an output buffer. A [Formula: see text]-boosted technique is employed within the CTLE for bandwidth and gain enhancement, while the TIA leverages a super source follower (SSF) structure to combat parasitic output node issues. By adjusting the tunable structures in the circuit, the proposed AFE can achieve variable DC gain at 14 GHz. Simulation results reveal that the AFE can compensate for the channel loss at the 14 GHz Nyquist frequency, delivering eye diagram spreads of approximately 0.85 UI and 0.78 UI at 14 Gb/s and 28 Gb/s, respectively. The complete post-simulation layout area is only 0.0026[Formula: see text]mm2. Operating with a power consumption of 10.5[Formula: see text]mW, the AFE exhibits an exceptional FoM of 11.8 pJ/bit/dB.