A 14-Bit Oversampled SAR ADC With Mismatch Error Shaping and Analog Range Compensation-Reference-Cited by-同舟云学术

A 14-Bit Oversampled SAR ADC With Mismatch Error Shaping and Analog Range Compensation

Published:2023-05 Issue:5 Volume:70 Page:1719-1723
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Shen Yuting¹^ORCID,Li Hanyue¹^ORCID,Bindra Harijot Singh²^ORCID,Cantatore Eugenio¹^ORCID,Harpe Pieter¹^ORCID

Affiliation:

1. Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, The Netherlands

2. Integrated Circuit Design Group, Faculty of Electrical Engineering, Mathematics and Computer Science, University of Twente, Enschede, The Netherlands

Funder

Dutch Research Council

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/10124122/10077761.pdf?arnumber=10077761

Reference9 articles.

1. A 103-dB SFDR Calibration-Free Oversampled SAR ADC With Mismatch Error Shaping and Pre-Comparison Techniques

2. A 7.3-μ W 13-ENOB 98-dB SFDR Noise-Shaping SAR ADC With Duty-Cycled Amplifier and Mismatch Error Shaping

3. A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise

4. 27.2 an oversampling SAR ADC with DAC mismatch error shaping achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOS

5. 11.1 An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1dB SNDR

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