A High ENOB 14-Bit ADC without Calibration-Reference-Cited by-同舟云学术

A High ENOB 14-Bit ADC without Calibration

Published:2024-01-31 Issue:3 Volume:13 Page:570
ISSN:2079-9292
Container-title:Electronics
language:en
Short-container-title:Electronics

Author:

Laoudias Costas¹^ORCID,Souliotis George²^ORCID,Plessas Fotis³

Affiliation:

1. Nanozeta Technologies, Larnaca CY-6043, Cyprus

2. Department of Electrical and Computer Engineering, University of the Peloponnese, 26334 Patras, Greece

3. Department of Electrical and Computer Engineering, University of Thessaly, 38334 Volos, Greece

Abstract

This paper presents an implementation of a 14-bit 2.5 MS/s differential Successive-Approximation-Register (SAR) analog-to-digital converter (ADC) to be used for sensing multiple analog input signals. A differential binary-weighted with split capacitance charge-redistribution capacitive digital-to-analog converter (CDAC) utilizing the conventional switching technique is designed, without using any calibration mechanism for fast power-on operation. The CDAC capacitor unit has been optimized for improved linearity without calibration technique. The SAR ADC has a differential input range 3.6 Vpp, with a SNDR of 80.45 dB, ENOB of 13.07, SFDR of 87.16 dB and dissipates an average power of 0.8 mW, while operating at 2.5 V/1 V for analog/digital power supply. The INL and DNL is +0.22/−0.34 LSB and +0.42/−0.3 LSB, respectively. A prototype ADC has been fabricated in a conventional CMOS 65 nm technology process.

Publisher

MDPI AG

Link

https://www.mdpi.com/2079-9292/13/3/570/pdf

Reference34 articles.

1. Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques;Tang;IEEE Trans. Circuits Syst. I Regul. Pap.,2022

2. Confalonleri, P., Zarnprogno, M., Girardi, F., Nicollini, G., and Nagari, A. (2004, January 23). A 2.7 mW 1MSps 10b analog-to-digital converter with built-in reference buffer and 1LSB accuracy programmable input ranges. Proceedings of the 30th European Solid-State Circuits Conference, Leuven, Belgium.

3. Agnes, A., Bonizzoni, E., Malcovati, P., and Maloberti, F. (2008, January 3–7). A 9.4-ENOB 1V 3.8 μW 100 kS/s SAR ADC with Time-Domain Comparator. Proceedings of the IEEE International Solid-State Circuits Conference—Digest of Technical Papers, San Francisco, CA, USA.

4. Srivastava, A., Yellampalli, S., and Golla, K. (2006, January 6–9). Delta-IDDQ Testing of a CMOS 12-Bit Charge Scaling Digital to Analog Converter. Proceedings of the 2006 49th IEEE International Midwest Symposium on Circuits and Systems, San Juan, PR, USA.

5. Allen, P.E., and Holberg, D.R. (2012). CMOS Analog Circuit Design, Oxford University Press.