A High ENOB 14-Bit ADC without Calibration
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Published:2024-01-31
Issue:3
Volume:13
Page:570
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ISSN:2079-9292
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Container-title:Electronics
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language:en
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Short-container-title:Electronics
Author:
Laoudias Costas1ORCID, Souliotis George2ORCID, Plessas Fotis3
Affiliation:
1. Nanozeta Technologies, Larnaca CY-6043, Cyprus 2. Department of Electrical and Computer Engineering, University of the Peloponnese, 26334 Patras, Greece 3. Department of Electrical and Computer Engineering, University of Thessaly, 38334 Volos, Greece
Abstract
This paper presents an implementation of a 14-bit 2.5 MS/s differential Successive-Approximation-Register (SAR) analog-to-digital converter (ADC) to be used for sensing multiple analog input signals. A differential binary-weighted with split capacitance charge-redistribution capacitive digital-to-analog converter (CDAC) utilizing the conventional switching technique is designed, without using any calibration mechanism for fast power-on operation. The CDAC capacitor unit has been optimized for improved linearity without calibration technique. The SAR ADC has a differential input range 3.6 Vpp, with a SNDR of 80.45 dB, ENOB of 13.07, SFDR of 87.16 dB and dissipates an average power of 0.8 mW, while operating at 2.5 V/1 V for analog/digital power supply. The INL and DNL is +0.22/−0.34 LSB and +0.42/−0.3 LSB, respectively. A prototype ADC has been fabricated in a conventional CMOS 65 nm technology process.
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering
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