A Non-Linear Successive Approximation Finite State Machine for ADCs with Robust Performance

Abstract

This work presents the detailed design of a Successive Approximation Analog to Digital Data Converter (SAR ADC) using bulk 180 nm CMOS IC technology. The focus of the study is on replacing the typical Successive Approximation Register array with a Finite State Machine. This converter features a fully differential and bipolar architecture, which leads to the logic SAR nonlinear behavior. A novel digital control logic mitigates the conversion errors through the conditions in the previous logic states. The logic scheme, in combination with a robust continuous comparator, demonstrates tolerance to Process, Voltage, and Temperature variations. The architecture does not include calibration or additional redundancies in post-layout simulations to emphasize the exclusive benefits of the new SAR logic. The proposed SAR ADC achieves a 14.07 effective number of bits with 7.04 fJ/conversion step Walden figure of merit in biomedical applications.