Parallel-Prefix Adder in Spin-Orbit Torque Magnetic RAM for High Bit-Width Non-Volatile Computation-Reference-Cited by-同舟云学术

Parallel-Prefix Adder in Spin-Orbit Torque Magnetic RAM for High Bit-Width Non-Volatile Computation

Published:2023-02 Issue:2 Volume:70 Page:761-765
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Li Ximing¹^ORCID,Jin Xing¹^ORCID,Chen Weichong²^ORCID,Yin Ningyuan³,Yu Zhiyi³^ORCID

Affiliation:

1. School of Electronics and Information Technology, Sun Yat-sen University, Guangzhou, China

2. School of Microelectronics Science and Technology, Sun Yat-sen University, Zhuhai, China

3. Guangdong Provincial Key Laboratory of Optoelectronic Information Processing Chips and Systems, School of Microelectronics Science and Technology, Sun Yatsen University, Zhuhai, China

Funder

National Key Research and Development Program of China

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/10032206/09919262.pdf?arnumber=9919262

Reference18 articles.

1. A Regular Layout for Parallel Adders

2. Compact Model for Spin–Orbit Magnetic Tunnel Junctions

3. STT-MRAM Design Technology Co-optimization for Hardware Neural Networks

4. Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity

5. Nanosecond-Timescale Low Energy Switching of In-Plane Magnetic Tunnel Junctions through Dynamic Oersted-Field-Assisted Spin Hall Effect

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1. CiTST-AdderNets: Computing in Toggle Spin Torques MRAM for Energy-Efficient AdderNets;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

2. Logic-in-Memory Based on Majority Gates With Voltage-Gated SOT-MRAM Crossbar Arrays;IEEE Transactions on Circuits and Systems II: Express Briefs;2023