Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity-Reference-Cited by-同舟云学术

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Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity

Published:2017-10-01 Issue:10 Volume:66 Page:1824-1830
ISSN:0018-9340
Container-title:IEEE Transactions on Computers
language:
Short-container-title:IEEE Trans. Comput.

Author:

Pudi Vikramkumar,Sridharan K.,Lombardi Fabrizio

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Link

http://xplorestaging.ieee.org/ielx7/12/8026540/07909019.pdf?arnumber=7909019

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3. A Novel Non-Voltatile Magnetic Majority Gate with Voltage-Gated Spin-Orbit Torque Magnetic Tunnel Junction Cascaded in Series for Low Power and High Reliability;2023 IEEE 23rd International Conference on Nanotechnology (NANO);2023-07-02

4. An Accelerated Variable Stage Size Carry Skip Adder Realization Using 1S1R Resistive Memory;International Journal of Information Technology & Decision Making;2023-05-23

5. Design of an Approximate Multiplier with Time and Power Efficient Approximation Methods;Journal of Circuits, Systems and Computers;2023-03-31

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