A 1.1-pJ/b 8-to-16-Gb/s Receiver With Stochastic CTLE Adaptation-Reference-Cited by-同舟云学术

A 1.1-pJ/b 8-to-16-Gb/s Receiver With Stochastic CTLE Adaptation

Published:2023-02 Issue:2 Volume:70 Page:381-385
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Shim Minkyo¹^ORCID,Lee Kwang-Hoon¹^ORCID,Roh Seungha¹^ORCID,Park Kwanseo²^ORCID,Jeong Deog-Kyoon¹^ORCID

Affiliation:

1. Department of Electrical and Computer Engineering and the Inter-University Semiconductor Research Center, Seoul National University, Seoul, South Korea

2. Department of System Semiconductor Engineering and the School of Electrical and Electronics Engineering, Yonsei University, Seoul, South Korea

Funder

Inter-University Semiconductor Research Center (ISRC) of Seoul National University and Samsung Electronics Company Ltd

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/10032206/09913896.pdf?arnumber=9913896

Reference12 articles.

1. Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in $5~\mu$ s

2. 6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS

3. A 32-Gb/s 3.53-mW/Gb/s Adaptive Receiver AFE Employing a Hybrid CTLE, Edge-DFE and Merged Data-DFE/CDR in 65-nm CMOS

4. 0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link

5. 6.8 A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-08

2. A Linearity Improved Equalizers for Short-Channel Communication Links;2024 35th Irish Signals and Systems Conference (ISSC);2024-06-13

3. Artificial Neural Network Based on Memristive Circuit for High-Speed Equalization;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-04

4. Differential Evolution-Based Adaptation Algorithm for Multistage Continuous-Time Linear Equalizer;IEEE Transactions on Components, Packaging and Manufacturing Technology;2023-12

5. An Aging Small-Signal Equivalent Circuit Modeling Method for InP HBT;IEEE Transactions on Device and Materials Reliability;2023-12